Verik is a hardware description language for designing and verifying digital integrated circuits. The goal of Verik is to enable the modern IDE workflow to bridge the technology gap between hardware and software development. Verik aims to be an interoperable drop-in replacement for SystemVerilog that leverages the modern software stack to improve productivity. Verik builds upon Kotlin, a modern, general-purpose programming language with a clean and expressive syntax. Verik is Kotlin reinterpreted with the semantics of a hardware description language. It is translated to SystemVerilog by the Verik compiler. The translation is direct, typically with one-to-one correspondence between the input and output source files. Verik generates readable SystemVerilog similar to what an engineer would have written. Verik is an open source project under the Apache License, Version 2.0.