Package io.verik.core

Core library for the Verik hardware description language.

Annotations

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annotation class Assert

(UNIMPLEMENTED) Annotates assertion properties.

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annotation class Com

Annotates combinational action blocks or combinationally assigned properties. It is executed when the value of its contents change and is used to model combinational logic. They correspond to SystemVerilog always_comb blocks.

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annotation class Cons

Annotates randomization constraints in a Class. Construct a constraint with the c function.

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annotation class Cover

Annotates cover properties, cover points, and cover crosses.

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annotation class Entry

Annotates that a declaration is an entry point for compilation. By default, all entry points are elaborated. If dead code elimination is enabled, declarations that are not reachable from any entry point are eliminated.

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annotation class In

Annotates input ports of a component. Mutable input ports are declared as var. Immutable input ports are declared as val and must be assigned a constant expression when instantiated.

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annotation class Inj

Inject a string literal directly as SystemVerilog.

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annotation class Make

Annotates component instantiations. We can instantiate a component with either positional port connections or named port connections.

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annotation class Out

Annotates output ports of a component. Output ports must be declared as var.

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annotation class Rand

Annotates that a property in a Class should be randomized.

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annotation class Randc

Annotates that a property in a Class should be randomized cyclically. The property cycles through all values within its range before repeating.

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annotation class Run

Annotates run action blocks. Run action blocks are started at the beginning of the simulation and are executed only once during the entire simulation. They correspond to SystemVerilog initial blocks.

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annotation class Seq

Annotates sequential action blocks or sequentially assigned properties. It is executed when its event expression is triggered and is used to model sequential logic. Sequential action blocks must contain an on expression and sequentially assigned properties must contain an oni expression to specify their event expressions. They correspond to SystemVerilog always_ff blocks.

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annotation class Task

Annotates tasks. Unlike functions, tasks are never synthesizable and can consume simulation time.

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annotation class Verik

Annotates Verik source files. This enables inspections by the Verik IntelliJ plugin.

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annotation class Wire

Annotates bidirectional wire ports of a component. Wire ports must be declared as var.

Type Parameters

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typealias ADD<N, M> = *

Adds the cardinals N and M.

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typealias AND<X, Y> = *

Logical and of the cardinals X and Y. X and Y must take the value of either zero or one.

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typealias DEC<N> = *

The cardinal N decremented by one.

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typealias DIV<N, M> = *

Divides the cardinals N and M

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typealias EXP<N> = *

Exponential base two of the cardinal N.

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typealias FALSE = *

Cardinal of value zero representing logical false.

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typealias IF<X, Y, Z> = *

Evaluates to the cardinal Y if the cardinal X is one and the cardinal Z otherwise. X must take the value of either zero or one.

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typealias INC<N> = *

The cardinal N incremented by one.

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typealias LOG<N> = *

Ceiling logarithm base two of the cardinal N.

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typealias MAX<N, M> = *

Takes the maximum of the cardinals N and M.

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typealias MIN<N, M> = *

Takes the minimum of the cardinals N and M.

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typealias MUL<N, M> = *

Multiplies the cardinals N and M.

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typealias NOT<X> = *

Logical not of the cardinal X. X must take the value of either zero or one.

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typealias OF<N> = *

The cardinal N. Used for shielding type parameters from the Kotlin type system.

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typealias OR<X, Y> = *

Logical or of the cardinals X and Y. X and Y must take the value of either zero or one.

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typealias SUB<N, M> = *

Subtracts the cardinals N and M.

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typealias TRUE = *

Cardinal of value one representing logical true.

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typealias WIDTH<N> = *

Width of the binary representation of the cardinal N. Equivalent to LOG<INC<N>>.

Types

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class AssociativeArray<K, V>

An associative array of elements with keys of type K and values of type V. They correspond to SystemVerilog associative arrays.

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abstract class Class

Base class for all user defined classes. Classes that inherit from Class correspond to SystemVerilog classes.

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abstract class ClockingBlock : Component

A clocking block to bundle signals synchronized on an event. Clocking blocks can be instantiated in modules and module interfaces. They correspond to SystemVerilog clocking blocks.

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class Cluster<N : *, T> : Component, Iterable<T>

A cluster of type T and size N. Clusters can be used to declare multiple components. Construct a cluster with the cluster function. Clusters are statically elaborated by the compiler.

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abstract class Component

Components are statically instantiated hardware that may have ports. They are declared with the @Make annotation.

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class Constraint

Randomization constraint for random properties of classes. Constraints are annotated with Cons and constructed with the c function.

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class CoverCross

A cover cross within a cover group that crosses a number of cover points. Construct a cover cross with the cc function.

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abstract class CoverGroup

A cover group that specifies a coverage model. Cover groups may contain cover points and cover crosses.

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class CoverPoint

A cover point within a cover group that specifies a value to be covered. Construct a cover point with the cp function.

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class DynamicArray<E>

A dynamic array of elements of type E. They correspond to SystemVerilog dynamic arrays.

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class Event

A simulation event.

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class Mailbox<T>

A mailbox of type T that is synchronized across processes. They correspond to SystemVerilog mailboxes.

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abstract class Module : Component

Module that may be synthesized to hardware. They correspond to SystemVerilog modules.

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abstract class ModuleInterface : Component

A module interface that carries signals between modules. Module interfaces can contain module ports to control signal direction. They correspond to SystemVerilog interfaces.

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abstract class ModulePort : Component

A module port to bundle signals in module interfaces and assign directionality. They correspond to SystemVerilog modports.

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class Packed<N : *, E> : Iterable<E>

A packed array of size N of elements of type E. They correspond to SystemVerilog packed arrays.

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class Queue<E> : Iterable<E>

A queue of elements of type E. They correspond to SystemVerilog queues.

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class Sbit<N : *>

Represents a sequence of N bits that is signed. They correspond to SystemVerilog packed signed logic.

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class Sequence

(UNIMPLEMENTED) A boolean expression evaluated over a single or multiple clock cycles. Sequences are used to define assertion properties and cover properties.

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abstract class Struct

The base class of all structs. They corresponds to SystemVerilog packed structs.

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class Time

Simulation time. They correspond to the SystemVerilog type time. The current simulation time can be found with the time function.

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class Ubit<N : *>

Represents a sequence of N bits that is unsigned. They correspond to SystemVerilog packed logic.

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abstract class Union

The base class of all unions. They correspond to SystemVerilog packed unions. All members of the union must have the same width.

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class Unpacked<X : *, E> : Iterable<E>

An unpacked array of size X of elements of type E. They correspond to SystemVerilog unpacked arrays.

Functions

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fun <X : *> b(): Boolean

Returns the value of the cardinal X as a Boolean. X must take the value of either zero or one.

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fun c(vararg conditions: Boolean): Constraint

Construct a randomization constraint from conditions.

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fun cat(vararg values: Any): Ubit<*>

Returns the concatenation of the values. values should not be empty.

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fun cc(x: CoverPoint, y: CoverPoint, vararg bins: String): CoverCross

Construct a CoverCross for cover points x and y. Optionally, specify the bins to be used. bins will be injected as SystemVerilog.

fun cc(x: CoverPoint, y: CoverPoint, z: CoverPoint, vararg bins: String): CoverCross

Construct a CoverCross for cover points x, y, and z. Optionally, specify the bins to be used. bins will be injected as SystemVerilog.

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fun <T> cluster(size: Int, instantiator: (Int) -> T): Cluster<*, T>

Instantiate a Cluster of type T with size members. size must be a compile time constant.

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fun cp(value: Any, vararg bins: String): CoverPoint

Construct a CoverPoint for value. Optionally, specify the bins to be used. bins will be injected as SystemVerilog.

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fun delay(value: Int)

Delay for value time steps.

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fun error(message: String)

Logs message with severity error.

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fun exp(value: Int): Int

Returns the exponential base two of value.

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fun fatal(): Nothing

Exits the simulation with an error status.

fun fatal(message: String): Nothing

Logs message with severity fatal and exits the simulation with an error status.

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fun <T> fill0(): T

Construct a value of type T with all bits set to false.

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fun <T> fill1(): T

Construct a value of type T with all bits set to true.

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fun <T> fillx(): T

Construct a value of type T with all bits set to unknown.

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fun <T> fillz(): T

Construct a value of type T with all bits set to floating.

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fun finish(): Nothing

Exits the simulation with no error status.

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fun forever(action: () -> Unit)

Loop action forever.

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fun fork(action: () -> Unit)

Spawn the process action and execute it concurrently with the parent process. To wait until all immediate child processes have terminated use join.

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fun Boolean.hasx(): Boolean

(UNIMPLEMENTED) Returns true if the boolean is unknown.

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fun Boolean.hasxz(): Boolean

(UNIMPLEMENTED) Returns true if the boolean is unknown or floating.

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fun Boolean.hasz(): Boolean

(UNIMPLEMENTED) Returns true if the boolean is floating.

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fun <N : *> i(): Int

Returns the value of cardinal N as an integer.

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fun <T> imp(): T

Represents a value that is imported from SystemVerilog. It is generated by the importer and should not be used directly.

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fun info(message: String)

Logs message with severity info.

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fun inj(content: String)

Inject content directly as a SystemVerilog statement. To inject an expression inline use inji.

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fun <T> inji(content: String): T

Inject content directly as an inline SystemVerilog expression. The injected expression has type T. To inject a statement use inj.

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fun join()

Wait until all immediate child processes spawned by fork have terminated.

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fun log(value: Int): Int

Returns the ceiling logarithm base two of value.

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fun max(vararg values: Sbit<*>): Sbit<*>
fun max(vararg values: Ubit<*>): Ubit<*>

Returns the maximum of the values. values should have at least two arguments

fun max(vararg values: Int): Int

Returns the maximum of the values. values should have at least two arguments.

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fun min(vararg values: Sbit<*>): Sbit<*>
fun min(vararg values: Ubit<*>): Ubit<*>
fun min(vararg values: Int): Int

Returns the minimum of the values. values should have at least two arguments

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fun monitor(message: String)

Prints the given message at the end of each time step if its value has changed. Only one monitor call can be active at any time.

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fun <T> nc(): T

Represents a value that is not connected in port connections or property declarations.

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fun negedge(value: Boolean): Event

Returns the event corresponding to the negative edge transition of value.

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fun on(vararg events: Event, block: () -> Unit)

Trigger a sequential action block on events. events should not be empty.

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fun <T> oni(vararg events: Event, block: () -> T): T

Inline form of on. Trigger a sequentially assigned property on events. events should not be empty.

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fun <T> optional(value: Boolean, instantiator: () -> T): T?

Conditionally instantiate T based on value. value must be a compile time constant.

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fun pack(value: Any): Ubit<*>

(UNIMPLEMENTED) Pack value as a Ubit.

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fun posedge(value: Boolean): Event

Returns the event corresponding to the positive edge transition of value.

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fun q(value: Boolean): Sequence

(UNIMPLEMENTED) Construct a Sequence that evaluates value on the current cycle.

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fun random(): Int

Returns a random integer.

fun random(max: Int): Int

Returns a random integer from 0 to max exclusive.

fun random(min: Int, max: Int): Int

Returns a random integer from min inclusive to max exclusive.

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fun randomBoolean(): Boolean

Returns a random Boolean.

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fun <N : *> randomUbit(): Ubit<N>

Returns a random Ubit of width N.

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fun <N : *> rep(value: Any): Ubit<*>

Returns value replicated N times.

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fun s(value: Int): Sbit<*>
fun s(value: String): Sbit<*>

Construct a Sbit out of the constant value.

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fun <N : *> s0(): Sbit<N>

Construct a Sbit with all bits set to false.

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fun <N : *> s1(): Sbit<N>

Construct a Sbit with all bits set to true.

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fun strobe(message: String)

Prints the given message at the end of the current time step.

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fun <N : *> sx(): Sbit<N>

(UNIMPLEMENTED) Construct a Sbit with all bits set to unknown.

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fun <N : *> sz(): Sbit<N>

(UNIMPLEMENTED) Construct a Sbit with all bits set to floating.

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fun <T> t(): String

Returns the SystemVerilog representation of type T. This should only be used in injected string literals to inject the type T.

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fun time(): Time

Returns the current simulation time.

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fun <N : *> Boolean.toSbit(): Sbit<N>

Converts this value to an Sbit of width N. The value is extended with sign extension.

fun <N : *> Int.toSbit(): Sbit<N>

Convert this value to an Sbit of width N.

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fun <N : *> Boolean.toUbit(): Ubit<N>

Converts this value to a Ubit of width N. The value is extended with zero extension.

fun <N : *> Int.toUbit(): Ubit<N>

Convert this value to a Ubit of width N.

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fun <N : *> u(): Ubit<*>

Construct a Ubit out of the cardinal N.

fun u(value: Int): Ubit<*>
fun u(value: String): Ubit<*>

Construct a Ubit out of the constant value.

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fun <N : *> u0(): Ubit<N>

Construct a Ubit with all bits set to false.

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fun <N : *> u1(): Ubit<N>

Construct a Ubit with all bits set to true.

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fun <T> unpack(value: Ubit<*>): T

(UNIMPLEMENTED) Unpack value to type T.

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fun <N : *> ux(): Ubit<N>

Construct a Ubit with all bits set to unknown.

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fun <N : *> uz(): Ubit<N>

Construct a Ubit with all bits set to floating.

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fun wait(cb: ClockingBlock)

Wait until the clocking block event occurs.

fun wait(event: Event)

Wait until event occurs.

fun wait(value: Boolean)

Wait until value is true.

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fun warning(message: String)

Logs message with severity warning.

Properties

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val floating: Boolean

Floating boolean value. Also referred to as the z value.

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val unknown: Boolean

Unknown boolean value. Also referred to as the x value.