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· 4 min read

We implement a RISC-V core in Verik based on the PicoRV32 project. PicoRV32 is a CPU core that supports the RISC-V RV32IMC instruction set. On top of the base RV32I instruction set, it implements the M-extension for integer multiplication and division and the C-extension for compressed instructions. It is configurable with an optional interrupt controller, single or two-cycle ALU, and single or dual-port register file.

· 5 min read

The UVM is the standard framework for writing constrained random test benches in SystemVerilog. It consists of a set of SystemVerilog classes that make use of OOP principles to standardize test bench structure and improve code reuse across projects. We implement an example from The UVM Primer that uses UVM transactions to verify an ALU. Drivers, monitors, and scoreboards that extend UVM classes are constructed directly in Verik by importing the UVM.

· 4 min read

Verik can be used for FPGA design with the Xilinx Vivado toolchain. Vivado WebPACK can be installed for free and has all the functionality required to simulate and synthesize FPGA designs. In this project we build an audio spectrum analyzer with an FFT on the Nexys 4 FPGA board and visualize the output on a VGA display.