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Verik is a hardware description language (HDL) for designing and verifying digital integrated circuits. The goal of Verik is to enable the modern IDE workflow to bridge the technology gap between hardware and software development. Verik aims to be an interoperable drop-in replacement for SystemVerilog that leverages the modern software stack to improve productivity. Verik builds upon Kotlin, a modern general-purpose programming language with a clean and expressive syntax. Verik is Kotlin reinterpreted with the semantics of an HDL. It can directly make use of tools built for the vibrant Kotlin ecosystem, such as the widely used IntelliJ IDEA IDE.

The Verik toolchain consists of two parts, the compiler and the importer. It serves to bridge the gap between the Kotlin and SystemVerilog environments. Verik is translated to SystemVerilog by the compiler. Conversely, SystemVerilog declarations can be imported into the Kotlin environment with the importer. This allow us to make use of SystemVerilog libraries such as the UVM directly in Verik. It also reduces the barriers to adoption by allowing a mix of Verik and SystemVerilog to coexist in the same code base. Users are able to immediately benefit from the productivity gains of Verik without having to build out new infrastructure from the ground up.


Verik is designed with the Principle of Least Astonishment in mind. Most language concepts such as packages, classes, and functions are carried over directly from Kotlin. As such, the Kotlin documentation is a good starting point for understanding Verik.

An example of a Verik adder module, alongside with the generated SystemVerilog, is shown below. The translation is direct, typically with one-to-one correspondence between the input and output source files. The names of declarations are preserved by the translation process. Verik generates readable SystemVerilog similar to what an engineer would have written.

Verik Adder

class Adder(
@In var clk: Boolean,
@In var a: Ubit<`8`>,
@In var b: Ubit<`8`>,
@Out var x: Ubit<`8`>
) : Module() {

fun seq() {
on(posedge(clk)) {
x = a + b

SystemVerilog Adder

module Adder(
input logic clk,
input logic [7:0] a,
input logic [7:0] b,
output logic [7:0] x,

always_ff @(posedge clk) begin : seq
x <= a + b;
end : seq


Verik is an open source project under the Apache License, Version 2.0. It was initially developed as a master's thesis project at the Massachusetts Institute of Technology. The white paper summarizing the high-level design of Verik and the comparison to other HDLs can be found here.